Hacker Newsnew | past | comments | ask | show | jobs | submitlogin

But we can’t go much smaller can we? Totally not well versed in the chip space, so what can we expect?


A usual reminder that we're not getting smaller. This is marketting speech, transistor gates are stuck at 20ish nanometers.

What's still increasing is transistor density, but "Dennard's Scaling" is dead. we stopped decreasing voltages some time ago.

We have more transistors, so we can make smarter chips. but we can't turn them on at the same time ("dark silicon"), we don't want to melt the chips.

Short of using other materials such as GaN, frequency won't really go above 5 GHz.

There remain plenty of ways to improve performance though: improvements to system architecture (distributed, non von neumann, changing the ISA), compilers, etc. Adiabatic computing, 3D integration, carbon nanotubes, tri-gate transistors, logic in memory, "blood" (cooling + power) and other microfluiduc advances, modularization with chiplets.

The "simple" Dennard's scaling is over though, and we need to move beyond CMOS and Von Neumann to really leverage increasing density without melting away.


> A usual reminder that we're not getting smaller. This is marketting speech, transistor gates are stuck at 20ish nanometers.

A quick perusal of WikiChip seems to suggest that this isnt true. Pretty much everything is getting smaller, including Fin pitch which should directly affect transistor size (not an EE, certainly could be wrong there). You're absolutely right that terms like "7nm" have become decoupled from a specific measurement and are largely marketing terms, though.

https://en.wikichip.org/wiki/10_nm_lithography_process

https://en.wikichip.org/wiki/7_nm_lithography_process


> You're absolutely right that terms like "7nm" have become decoupled from a specific measurement and are largely marketing terms, though

Everybody says this, if I've read it once on HN, I've read it a million times.

But it bothered me, why should it be difficult to come up with a reasonably meaningful number? Just find out how many transistors can be placed in a given area, pretend they are laid out in a square, and find the number on a side, to calculate the linear density.

Well, I looked up and calculated this for several chips/processes, and I found that the number was consistently around 10 times the published figure, in nm.

The further interesting thing I discovered is that this seemed to go way back with no particular change in the ratio.

So it appears to me that the "decoupling" of the number from reality is a myth; it's not "real" but it's the same ratio it's always been.

But then, there's no obvious (to me) reason why a realistic number is out of the question, either.


> The further interesting thing I discovered is that this seemed to go way back with no particular change in the ratio.

Exactly, as that's more or less what "process node" refers to today. I guess they don't want to change the metric as some could be confused by it.

> But it bothered me, why should it be difficult to come up with a reasonably meaningful number? Just find out how many transistors can be placed in a given area, pretend they are laid out in a square, and find the number on a side, to calculate the linear density.

There are plenty of other metrics. As usual, measuring only one number hides half the story. A process node is characterized by gate leakage and capacitance among others, for the electrical characteristics. Then, more meaningful surface area metrics are the size of an actual logic cell, like SRAM or a flipflop. Some processes lend themselves to optimizations that wouldn't be visible if just placing transistors side by side.


Sorry, I should have been clearer that I was specifically talking about gate length.

Transistor size (occupied area) decreases, but that's mainly because FinFET uses vertical gates, not planar technology, so you can stack them closer (well, it also has other advantages).

Thanks for the links, that's an interesting website. If you look at the 10nm one, they explicitly call out what I said, and write 20nm for gate length (tunneling losses start increasing a lot if you reduce that, so I'm not sure how to read the 7nm page, maybe they got it wrong?)

In any case, process node once reffered to gate length; it doesn't anymore: https://en.wikichip.org/wiki/technology_node

We're not getting smaller, not that we couldn't (e-beam and ALD give us atomic resolution), but because it's useless (at that point, gate leakage and doping issues become hard to overcome). Instead we're improving precision, and our control along the 3rd dimension. Integration technologies are also progressing: flip-chip, TSVs. That will allow features like integrated HBM, on-chip lasers and photonics circuits, etc.


> 3D integration

In case anyone missed it, AMD announced a basic "3D" design last month

https://www.hpcwire.com/2021/06/02/amd-introduces-3d-chiplet...

Essentially AMD "stacked a 64MB 7nm SRAM directly on top of each core complex, tripling the L3 cache available to the Zen 3 cores."

I am excited to see what comes next!


Jim Keller believes that at least 10-20 years of shrinking is possible [1].

[1] https://www.youtube.com/watch?v=Nb2tebYAaOA&t=1800


the last 20 years people had serious doubts on breaching 7nm (whatever the figure means today) but, and even if Keller is a semigod (pun half intended) .. I'm starting to be seriously dubious on 20 years of continued progress.. unless he means a slow descent to 1-2nm .. or he's thinking sub-atomic electronics / neutronics / spintronics (in which case good on him).


Jim Keller is legend in microarchitecture design, not in process technology. All his arguments seem to be just extrapolating from the past.

Process engineers&material scientists seem more cautious. I'm sure shrinking goes but gains are smaller from each generation.

TSMC 3nm Process is something like 250 MTr/mm² and single digit performance increase and 15-30% power efficiency increase compared to older prosess.


It does, though, reduce heat, right? Which ultimately is more cores per socket. Which hits the thing that actually matters...price/performance.


Yes. But that's a huge decline compared to even recent past.

Performance increases from generation to generation used to be much faster. TSMC's N16 to N7 was still doubling or almost doubling performance and price/performance over the long term. N5 to N3 is just barely single digits.

Every fab generation is more expensive than in the past. Soon every GIGAFAB costs $30 billion while technology risk increaseses.


That’s true, but because Moore’s Law has slowed, you’ll be able to amortize that $30 billion over a longer time.


> because Moore’s Law has slowed

Not sure that is really true based on the data. Remember, Moore's law says the number of transistors in an IC doubles every two years, which doesnt necessarily mean a doubling of performance. For a while in the 90's, performance was also doubling every two years, but that was largely due to frequency scaling.

https://upload.wikimedia.org/wikipedia/commons/0/00/Moore%27...


To be precise, Moore’s Law says the number of transistors per unit cost doubles (every two years). https://newsroom.intel.com/wp-content/uploads/sites/11/2018/...

A lot of the new processes have not had the same cost reductions. Also, some increase in transistor count is due to physically larger chips. Also, you have “Epyc Rome” on that graph, which actually isn’t a single chip but uses chiplets.


Yeah and after you have a working $30B fab, how many people are going to follow you to build one?

The first one built will get cheaper to run every year - it will pay for itself by the time a second company even tries to compete. The first person to the "final" node will have a natural, insurmountable monopoly.

You could extract rent basically forever after that point.


I don't think we'll see a final node in our lifetimes. Improvements are slowing down and will become a trickle, but that doesn't mean research stops entirely.

Consider other mature technology, like the internal combustion engine. ICEs have been improved continuously, though the changes have become marginal as the technology matured. However, if research and improvements on ICEs ends entirely it's not because the technology has been fully explored but because they're obsoleted by electric cars.


I thought the drivers of cost are lots of design work, patents, trade secrets etc. involved with each process. If there’s a “final” node, those costs should decrease over time and eventually become more of a commodity.


That's only true if the supply satisfies demand.


The video that was posted goes into that (30min mark) and seems to reflect what you are saying.


he might know some about the material science behind things but yeah, that said I'd like to hear about actual semi/physics researchers on the matter


If we ever figure out a way to make caron nanotube transistors in volume, expect another 50 years of Moore's law.


Since the "nm" numbers are just marketing anyway, I think they don't mean much in regards to how small we can go. We can go small until the actual smallest feature size hits physical limitations, which is so decoupled from the nm number that we can't possibly tell how close "7nm" is (well, I mean, we can, there's a cool youtube video showing the transistors and measuring feature size with a scanning electron microscope, but I mean we can't tell just from the naming/marketing).


Check out the lex fridman Jim Keller podcast on YouTube


On the same podcast you can find David Patterson (known for writing some widely used computer architecture books), who disputes this claim.

https://www.youtube.com/watch?v=naed4C4hfAg

At 1:20:00


David Patterson is not disputing that there's decades left of transistor shrinking, he's just saying that the statement of "transistor count doubling every 2 years" doesn't hold up empirically.

David Patterson is saying he considers Moore's Law is dead because the current state of say, "transistor count doubling every three years" doesn't match the Moore's Law exact statement.

In other words, he is simply being very pedantic about his definition. I can see where he's coming from with that argument.


It's more than that though as it's important to remember why Moore made his law in the first place.

The rough organizational structure of a VLSI team that makes CPUs is the following pipeline:

architecture team -> team that designs the circuits which implement the architecture -> team that manufactures the circuits

The law was a message to the architecture team that by the time your architecture gets to manufacture you should expect there to be ~2x the number of transistor you have today available, and that should influence your decisions when making trade-offs.

And that held for a long time. But, if you're in a CPU architecture team today, and you operate that way, you will likely be disappointed when it comes to manufacture. Therefore one should consider Moore's law dead when architecting CPUs.


I don’t think it’s irrelevant to look at changing timescale. If the law broke down to be 3 years, there isn’t any reason it won’t be 4, 5, or some other N years in the future.


Every 2 years


Right. But it is no longer 2 years so it’s not Moore’s Law any more.


And for those who don’t know, Jim Keller is a legend.

https://en.m.wikipedia.org/wiki/Jim_Keller_(engineer)


That was a nice watch! Thanks!


A revisit of how to do parallelism. Hopefully more successfully than Itanium and its compilers fared. The Mill CPU has some ideas there as well.


It was interesting working at microsoft next to some folks that were around in the Itanium days and worked on it. Hearing their stories and theories was really cool. I wonder if now is the time of alternative ISAs given that JIT and other technologies have gotten so good


We're already at the point where a transistor is a double-digit number of silicon atoms. The cost of each node shrink is growing at an insane rate.

The good times might be back for now - and don't get me wrong, I'm having a blast - but don't expect them to last for long. I think this is probably the last sputter of gas in the tank, not a return to the good times.


But what happens if we hit the final plateau, same processor speed (+ minor improvements) for the decades to come?


We start optimizing software, and then we start optimizing requirements, and then computing is finally finished, the same way spoons are finally finished.


Are spoons really finished? I am sure plenty of people are designing better/cheaper spoons today. I love looking at simple, everyday objects and look at how they evolved over time. Like soda cans, water bottles. Even what may be the oldest tool, the knife is constantly evolving. Better steels, or even ceramic, folding mechanisms for pocket knives, handle materials, and of course all the industrial processes that gets us usable $1 stainless steel knives.

Computers are the most complex objects man has created, there is no way it is going to be finished.


you can also optimize society because every time a human gets in the loop, trillions of cycles are wasted, and people / software / platforms are really far from efficient.

actually if companies and software were designed differently (with teaching too, basically an ideal context) you could improve a lot of things with 10x factors just from the lack of resistance and pain at the operator level


This is a really good point you make.

A simple example for me is how the ATM replaced the bank teller, but the ATM has been replaced with cards with chips in them. It’s a subtle, but huge change when magnified across society.


are chips an issue ?

having worked in various administrations, the time / energy / resources wasted due to old paper based workflow is flabbergasting

you'd think after 50 years of mainstream computing they'd have some kind of adequate infrastructure but it's really really sad (they still have paper inbox for internal mail routing errors)


Computing will never be finished like spoons in the software realm because software is like prose. It's a language where we write down our needs, wants, and desires, and instructions to obtain them, and those are always shifting.

I could definitely see standard classical computer hardware becoming a commodity though.

There will also be room for horizontal expansion for a LONG time. If costs drop through the floor then we could see desktops and servers with hundreds or thousands of 1nm cores.


The hardware will be finished. But the food we eat (the software) will keep changing.


You optimize software--which means more time/money to write software for a given level of functionality. More co-design of hardware and software, including more use of ASICs/FPGAs/etc. And stuff just doesn't get faster/better as easily so upgrade cycles are longer and potentially less money flows into companies creating hardware and software as a result. Maybe people start upgrading their phones every 10 years like they do their cars.

We probably have a way to go yet but the CMOS process shrink curve was a pretty magical technology advancement that we may not see again soon.


To some extent yes, but there's a lot of low hanging fruit.

Java is only just now getting value types, even though flattened value types are fundamental to getting good performance on modern CPUs. Much software is HTML and JavaScript which is so far from having value types it's not even worth thinking about. Simply recoding UIs from JS -> Java/Kotlin+value types would result in a big win without much productivity loss.


Transistor size is not the only factor in processing speed, architecture is also important. We will still be able to create specialised chips, like deep learning accelerators and such.


As already mentioned, there's plenty of innovation happening still with packaging, plus even on the IC level there's all kinds of possibilities for advancement: new transistor designs (to reduce power consumption or to increase density by decreasing spacing), monolithic 3D ICs (the vast majority of current 3D approaches are manufacturing multiple wafers or dies then wiring them together; if you can do it on a single wafer you can do a lot more movement between layers). Plus there's always the potential to move away from silicon to make transistors even smaller.

Away from the IC level itself we're only just starting to scratch the surface of optimisation algorithms for many NP-hard problems that occur in IC design, like floor plan arrangement.


advance packaging, chiplet, 3DFabric...etc


If history has taught us anything it's that technology won't stop evolving. And whenever humans thinks surely we've reached the peak of technological advancements, time proves us wrong. One thing is for sure, it's going to look very different from what we can imagine today.


Technology stagnated all the time in history. The pattern is new approach gets perfected resulting in ever smaller gains and different tradeoffs. Look at say rings where personal skill plays a larger role than the advancements in technology. We might be better at mining gold today, but that doesn’t translate into a better ring.

Include longevity as one of the points of comparison and a lot of progresses looks like a step back. Cheaper and doesn’t last as long has been a tradeoff people have been willing to make for thousands of years.


Technology also gets as good as necessary and not necessarily further, for long periods of time.

Babies have "colics", which are probably some kind of pain that we haven't identified yet, but because they go away on their own and parents are taught that they just have to deal with them, we still apply a medieval solution to the problem ("tough it out").

Rings seem to be the kind of problem where our current solution is good enough.

I don't foresee computing power to be the same. We'll want more and more of it.

So stagnation will be due to gaps in basic research, not due lack of interest.


I see that computing power is in high demand for quite some time to come.

I do believe there will be stagnation unless a different way is found. In the same way Henry Ford said people wanted a faster horse not a car.

And regarding travel, I would like to have faster, much faster transportation. However it hasn't come, yet. There seems to be a local optimum between costs and practicality.


> Look at say rings where personal skill plays a larger role than the advancements in technology.

What about advancements metallurgy? And to use an adjacent example, cold-pressed steel techniques increase the number of places steel can be used. (See here https://en.wikipedia.org/wiki/Cold-formed_steel#Hot-rolled_v...).

More often that not, technology enables trade-offs to be made that couldn't be before. Making something cheaper and more fragile does lose something, service life, and so on. In exchange the cheaper thing is now used more widely. Perhaps this more widespread use unlocks something that only a few expensive yet high-quality units could not. Think of smartphones and the resulting network effects.


18k Gold jewelry has been using 18 parts gold, 3 parts copper, and 3 parts silver for a long time.

In theory sure we could probably improve on it, but it works.




Consider applying for YC's Fall 2026 batch! Applications are open till July 27.

Guidelines | FAQ | Lists | API | Security | Legal | Apply to YC | Contact

Search: