Yes, a major pita. Mainly afraid of not groking the bus and driving the bus at the same time as the 68k. The working idea is to use a bunch of some sort of voltage translator chip (finding the right one for this is the pain point), and imposing constraints so that if the CPU is driving the address or data bus as signaled by e.g. /AS or the R/W signal, then the translators won't drive it. With a bunch of 74s or a CPLD in the 5v side.
I didn't have that one PDF, so I saved it for safe-keeping with my other 68k stuff. Thanks.
D lines and some signals need to be bidirectional. And I might even need to do bus mastering, so most signals would have to be.