I'm going to have to make assumptions on your semantics. I assume that OP(x) means that instruction OP uses data element x. Further, I assume that instructions on the same line are executed in parallel and before instructions on the next line.

OP1(f1)OP1(f2)

OP2(f3)OP2(f4)

Instruction level parallelism because OP1(f1) executes in parallel with OP1(f2) and OP2(f3) executes in parallel with OP2(f4).

OP1(f1)

OP1(f2)OP2(f3)

OP2(f4)

Instruction level parallelism because OP1(f2) executes in parallel with OP2(f3). (But, the schedule isn't as good as the first one.)

OP1(f1, f2)

OP2(f3, f4)

Data level parallelism because OP1 is applied to both f1 and f2. While this has the same result as the first example, a processor would achieve both in different ways. In the first example, the processor would have to fetch two instructions. It just so happens that both of those instructions are OP1. Then it would have to schedule both of those instructions, and it was luckily able to schedule them both at the same time.

The third example is different. In this case, the processor would fetch one instruction, but execute it on both f1 and f2 at the same time. That's why it's called SIMD: single instruction, multiple data. One instruction executes, but it modifies multiple data elements. In the first case, you had to fetch and execute an instruction for each data element.

Why bother distinguishing between them? Because this may also be possible:

OP1(f1, f2)OP2(f3, f4)

That is both data level parallelism and instruction level parallelism.